1. Field of the Invention
This invention relates to a memory controller adapted to temporarily store input video signals and read them out as occasion calls and also to a liquid crystal display apparatus using such a control.
2. Related Background Art
Known systems for temporarily storing video signals input from, for example, a personal computer and reading them out as occasion calls operate in a manner as described below by referring to FIG. 2 of the accompanying drawings. Firstly, the video input through input terminal 5 for the first frame is temporarily stored in frame memory 1 selected by demultiplexer 9. Then, the demultiplexer 9 switches to frame memory 8 to store the video input for the second frame there. At the same time, multiplexer 10 selects the frame memory 1 and reads out the video input for the first frame from there to output terminal 6.
Then, the demultiplexer 9 switches back to the frame memory 1 to store another video signal there and, at the same time, the multiplexer 10 selects the frame memory 8 and reads out the video input stored there to the output terminal 6. In this way, video signals are output continuously on a frame by frame basis by using two frame memories.
When a same image is to be displayed twice for flicker prevention and/or other purposes, each video signal is read out twice from the frame memory storing it at a rate twice as high as the rate of receiving image signals.
However, with such an arrangement, at least two frame memories, which is costly, have to be used to raise the cost of the entire system. When an image signal is read out twice, the rate of reading image signals is required to be twice as high as that of storing them in frame memories but it will be impossible to realize such a high rate particularly when image signals have to be received at an enormously high rate to improve the resolution of the displayed image.
Known techniques for controlling frame memories include the following.
Japanese Patent Application Laid-Open No. 6-275069 describes a method of carrying out a serial/parallel conversion for each input signal before it is written into a memory and then the signal read out from the memory is subjected to a parallel/serial conversion before it is output in order to achieve an FIFO operation. Japanese Patent Application Laid-Open Nos. 58-16343 and 60-159789 describe a technique of interposing an FIFO memory between an image memory and a parallel/serial converter. Japanese Patent Application Laid-Open No. 63-240620 describes a display technique using a buffer between an image memory and a parallel/serial converter. Japanese Patent Application Laid-Open No. 4-259079 describes an image reader comprising an FIFO memory and a parallel/serial converter. Japanese Patent Application Laid-Open No. 5-158447 describes a technique of improving the signal transfer rate by arranging an FIFO memory in a display data transfer section for transferring signals from a memory to a liquid crystal display in order to prevent flickers from appearing on the display screen. Finally, Japanese Patent Application Laid-Open No. 2-33672 describes an FIFO memory for inputting data to and outputting data from a serial read/write port.
However, it is not possible to realize a continuous signal writing/reading operation by means of a memory having a relatively small memory capacity with any of the above described known techniques.